Questions 2 : Assume there are three small caches, each consisting of four one-word blocks. On cache is direct-mapped, a second is two-way set-associative, and the third is fully associative. Find the number of hits for each cache organization given the following sequence of block addresses: 0, 8, 6, 5, 10, 15 and 8 are accessed twice in the same sequence. Make a tabular column as given below to show the cache content on each of columns as required. Show all the pass independently pass. Draw as many numbers Assume the writing policy is LRU. Memory location Hit/Mis Add as many columns as required
Answer:
Sequence of Block Addresses:
0, 8, 6, 5, 10, 15, 8 (accessed twice in the same sequence)
Cache Configurations:
- Direct-Mapped Cache: 4 blocks
- Two-Way Set-Associative Cache: 2 sets with 2 blocks each
- Fully Associative Cache: 4 blocks
Simulation:
Direct-Mapped Cache:
Access | Address | Index | Cache Content | Hit/Miss |
---|---|---|---|---|
1 | 0 | 0 | 0 | Miss |
2 | 8 | 0 | 8 | Miss |
3 | 6 | 2 | 8, 6 | Miss |
4 | 5 | 1 | 8, 6, 5 | Miss |
5 | 10 | 2 | 8, 10, 5 | Miss |
6 | 15 | 3 | 8, 10, 5, 15 | Miss |
7 | 8 | 0 | 8, 10, 5, 15 | Hit |
8 | 0 | 0 | 0, 10, 5, 15 | Miss |
9 | 8 | 0 | 8, 10, 5, 15 | Miss |
10 | 6 | 2 | 8, 6, 5, 15 | Miss |
11 | 5 | 1 | 8, 6, 5, 15 | Hit |
12 | 10 | 2 | 8, 10, 5, 15 | Miss |
13 | 15 | 3 | 8, 10, 5, 15 | Hit |
14 | 8 | 0 | 8, 10, 5, 15 | Hit |
Direct-Mapped Cache Hits: 3
Two-Way Set-Associative Cache:
Access | Address | Index | Set Content | Hit/Miss |
---|---|---|---|---|
1 | 0 | 0 | (0, -) | Miss |
2 | 8 | 0 | (0, 8) | Miss |
3 | 6 | 1 | (0, 8), (6, -) | Miss |
4 | 5 | 1 | (0, 8), (6, 5) | Miss |
5 | 10 | 0 | (10, 8), (6, 5) | Miss |
6 | 15 | 1 | (10, 8), (6, 15) | Miss |
7 | 8 | 0 | (10, 8), (6, 15) | Hit |
8 | 0 | 0 | (0, 8), (6, 15) | Miss |
9 | 8 | 0 | (0, 8), (6, 15) | Hit |
10 | 6 | 1 | (0, 8), (6, 15) | Hit |
11 | 5 | 1 | (0, 8), (5, 15) | Miss |
12 | 10 | 0 | (10, 8), (5, 15) | Miss |
13 | 15 | 1 | (10, 8), (5, 15) | Hit |
14 | 8 | 0 | (10, 8), (5, 15) | Hit |
Two-Way Set-Associative Cache Hits: 5
Fully Associative Cache:
Access | Address | Cache Content | Hit/Miss |
---|---|---|---|
1 | 0 | 0 | Miss |
2 | 8 | 0, 8 | Miss |
3 | 6 | 0, 8, 6 | Miss |
4 | 5 | 0, 8, 6, 5 | Miss |
5 | 10 | 8, 6, 5, 10 | Miss |
6 | 15 | 6, 5, 10, 15 | Miss |
7 | 8 | 5, 10, 15, 8 | Miss |
8 | 0 | 10, 15, 8, 0 | Miss |
9 | 8 | 15, 8, 0 | Hit |
10 | 6 | 8, 0, 6 | Miss |
11 | 5 | 0, 6, 5 | Miss |
12 | 10 | 6, 5, 10 | Miss |
13 | 15 | 5, 10, 15 | Miss |
14 | 8 | 10, 15, 8 | Miss |
Fully Associative Cache Hits: 1
Summary of Hits:
- Direct-Mapped Cache Hits: 3
- Two-Way Set-Associative Cache Hits: 5
- Fully Associative Cache Hits: 1
Here is the summary table for the cache contents and hits/misses for each access:
Access | Address | Direct-Mapped Cache | Hit/Miss | Two-Way Set-Associative Cache | Hit/Miss | Fully Associative Cache | Hit/Miss |
---|---|---|---|---|---|---|---|
1 | 0 | 0 | Miss | (0, -) | Miss | 0 | Miss |
2 | 8 | 8 | Miss | (0, 8) | Miss | 0, 8 | Miss |
3 | 6 | 8, 6 | Miss | (0, 8), (6, -) | Miss | 0, 8, 6 | Miss |
4 | 5 | 8, 6, 5 | Miss | (0, 8), (6, 5) | Miss | 0, 8, 6, 5 | Miss |
5 | 10 | 8, 10, 5 | Miss | (10, 8), (6, 5) | Miss | 8, 6, 5, 10 | Miss |
6 | 15 | 8, 10, 5, 15 | Miss | (10, 8), (6, 15) | Miss | 6, 5, 10, 15 | Miss |
7 | 8 | 8, 10, 5, 15 | Hit | (10, 8), (6, 15) | Hit | 5, 10, 15, 8 | Miss |
8 | 0 | 0, 10, 5, 15 | Miss | (0, 8), (6, 15) | Miss | 10, 15, 8, 0 | Miss |
9 | 8 | 8, 10, 5, 15 | Miss | (0, 8), (6, 15) | Hit | 15, 8, 0 | Hit |
10 | 6 | 8, 6, 5, 15 | Miss | (0, 8), (6, 15) | Hit | 8, 0, 6 | Miss |
11 | 5 | 8, 6, 5, 15 | Hit | (0, 8), (5, 15) | Miss | 0, 6, 5 | Miss |
12 | 10 | 8, 10, 5, 15 | Miss | (10, 8), (5, 15) | Miss | 6, 5, 10 | Miss |
13 | 15 | 8, 10, 5, 15 | Hit | (10, 8), (5, 15) | Hit | 5, 10, 15 | Miss |
14 | 8 | 8, 10, 5, 15 | Hit | (10, 8), (5, 15) | Hit | 10, 15, 8 | Miss |
- Direct-Mapped Cache Hits: 3
- Two-Way Set-Associative Cache Hits: 5
- Fully Associative Cache Hits: 1
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