//Hierarchical Inheritance
/*
A
|
---------
| |
B C
*/
#include <iostream.h>
#include <conio.h>
class A
{
protected:
int a;
};
class B : public A
{
protected:
int b;
public:
void getB()
{
cout << "Enter value A :";
cin >> a;
cout << "Enter value B :";
cin >> b;
}
void showB()
{
cout << endl << "Value A is :" << a;
cout << endl << "Value B is :" << b << endl;
}
};
class C : A
{
protected:
int c;
public:
void getC()
{
cout << endl << "Enter value A : ";
cin >> a;
cout << "Enter value C : ";
cin >> c;
}
void showC()
{
cout << endl << "Value A is : " << a;
cout << endl << "Value C is : " << c;
}
};
void main()
{
clrscr();
B obj1;
C obj2;
obj1.getB();
obj1.showB();
obj2.getC();
obj2.showC();
getch();
}
Questions 2 : Assume there are three small caches, each consisting of four one-word blocks. On cache is direct-mapped, a second is two-way set-associative, and the third is fully associative. Find the number of hits for each cache organization given the following sequence of block addresses: 0, 8, 6, 5, 10, 15 and 8 are accessed twice in the same sequence. Make a tabular column as given below to show the cache content on each of columns as required. Show all the pass independently pass. Draw as many numbers Assume the writing policy is LRU. Memory location Hit/Mis Add as many columns as required
Answer : Sequence of Block Addresses: 0, 8, 6, 5, 10, 15, 8 (accessed twice in the same sequence) Cache Configurations: Direct-Mapped Cache : 4 blocks Two-Way Set-Associative Cache : 2 sets with 2 blocks each Fully Associative Cache : 4 blocks Simulation: Direct-Mapped Cache: Access Address Index Cache Content Hit/Miss 1 0 0 0 Miss 2 8 0 8 Miss 3 6 2 8, 6 Miss 4 5 1 8, 6, 5 Miss 5 10 2 8, 10, 5 Miss 6 15 3 8, 10, 5, 15 Miss 7 8 0 8, 10, 5, 15 Hit 8 0 0 0, 10, 5, 15 Miss 9 8 0 8, 10, 5, 15 Miss 10 6 2 8, 6, 5, 15 Miss 11 5 1 8, 6, 5, 15 Hit 12 10 2 8, 10, 5, 15 Miss 13 15 3 8, 10, 5, 15 Hit 14 8 0 8, 10, 5, 15 Hit Direct-Mapped Cache Hits: 3 Two-Way Set-Associative Cache: Access Address Index Set Content Hit/Miss 1 0 0 (0, -) Miss 2 8 0 (0, 8) Miss 3 6 1 (0, 8), (6, -) Miss 4 5 1 (0, 8), (6, 5) Miss 5 10 0 (10, 8), (6, 5) Miss 6 15 1 (10, 8), (6, 15) Miss 7 8 0 (10, 8), (6, 15) Hit 8 0 0 (0, 8), (6, 15) Miss 9 8 0 (0, 8), (6, 15) Hit 10 6 1 (0, 8), (6, 15) Hit 11 5 1 (0, 8), (5, 15) M
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