/* j_3_p_9
Create a class Father that has height & color as data member. Create a class Mother that
has color & eyeColor as data member. Create a class child that will inherits the Father &
Mother class. (Multiple)
*/
#include <iostream.h>
#include <conio.h>
class father
{ public:
int h;
char fclr[10];
};
class mother
{
public:
char mclr[10], eyeclr[10];
};
class child : virtual public father, virtual public mother
{
void father()
{
cout << "Enter Father Height : ";
cin >> h;
cout << "Enter Father color : ";
cin >> fclr;
}
void mother()
{
cout << "Enter Mother color : ";
cin >> mclr;
cout << "Enter Mother eye color : ";
cin >> eyeclr;
}
void print()
{
cout << "Father Height is " << h << endl;
cout << "Father color is" << fclr << endl;
cout << "Mother color is " << mclr << endl;
cout << "Mother eye color is " << mclr;
}
};
void main()
{
clrscr();
child obj;
obj.father();
obj.mother();
obj.print();
getch();
}
Questions 2 : Assume there are three small caches, each consisting of four one-word blocks. On cache is direct-mapped, a second is two-way set-associative, and the third is fully associative. Find the number of hits for each cache organization given the following sequence of block addresses: 0, 8, 6, 5, 10, 15 and 8 are accessed twice in the same sequence. Make a tabular column as given below to show the cache content on each of columns as required. Show all the pass independently pass. Draw as many numbers Assume the writing policy is LRU. Memory location Hit/Mis Add as many columns as required
Answer : Sequence of Block Addresses: 0, 8, 6, 5, 10, 15, 8 (accessed twice in the same sequence) Cache Configurations: Direct-Mapped Cache : 4 blocks Two-Way Set-Associative Cache : 2 sets with 2 blocks each Fully Associative Cache : 4 blocks Simulation: Direct-Mapped Cache: Access Address Index Cache Content Hit/Miss 1 0 0 0 Miss 2 8 0 8 Miss 3 6 2 8, 6 Miss 4 5 1 8, 6, 5 Miss 5 10 2 8, 10, 5 Miss 6 15 3 8, 10, 5, 15 Miss 7 8 0 8, 10, 5, 15 Hit 8 0 0 0, 10, 5, 15 Miss 9 8 0 8, 10, 5, 15 Miss 10 6 2 8, 6, 5, 15 Miss 11 5 1 8, 6, 5, 15 Hit 12 10 2 8, 10, 5, 15 Miss 13 15 3 8, 10, 5, 15 Hit 14 8 0 8, 10, 5, 15 Hit Direct-Mapped Cache Hits: 3 Two-Way Set-Associative Cache: Access Address Index Set Content Hit/Miss 1 0 0 (0, -) Miss 2 8 0 (0, 8) Miss 3 6 1 (0, 8), (6, -) Miss 4 5 1 (0, 8), (6, 5) Miss 5 10 0 (10, 8), (6, 5) Miss 6 15 1 (10, 8), (6, 15) Miss 7 8 0 (10, 8), (6, 15) Hit 8 0 0 (0, 8), (6, 15) Miss 9 8 0 (0, 8), (6, 15) Hit 10 6 1 (0, 8), (6, 15) Hit 11 5 1 (0, 8), (5, 15) M
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