56. java.lang.String class

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7.Write a program to read a list containing item name, item code and cost interactively and produce a three-column output as shown below. NAME CODE COST Turbo C++ 1001 250.95 C Primer 905 95.70 ------------- ------- ---------- ------------- ------- ---------- Note that the name and code are left-justified and the cost is right-justified with a precision of two digits. Trailing zeros are shown.

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 /*J_4_P_8 Write a program to read a list containing item name, item code and cost interactively and produce a three-column output as shown below. NAME                CODE      COST ======================= Turbo C++        1001          250.95 C Primer              905           95.70 ------------- ------- ----------------- ------------- ------- ----------------- Note that the name and code are left-justified and the cost is right-justified with a precision of two digits. Trailing zeros are shown. */ #include <iostream.h> #include <iomanip.h> #include <string.h> #include <conio.h> class item {         char name[40];         int code;         float cost; public:         void get_data(char *n, int c, float co)...
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Questions 2 : Assume there are three small caches, each consisting of four one-word blocks. On cache is direct-mapped, a second is two-way set-associative, and the third is fully associative. Find the number of hits for each cache organization given the following sequence of block addresses: 0, 8, 6, 5, 10, 15 and 8 are accessed twice in the same sequence. Make a tabular column as given below to show the cache content on each of columns as required. Show all the pass independently pass. Draw as many numbers Assume the writing policy is LRU. Memory location Hit/Mis Add as many columns as required

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  Answer : Sequence of Block Addresses: 0, 8, 6, 5, 10, 15, 8 (accessed twice in the same sequence) Cache Configurations: Direct-Mapped Cache : 4 blocks Two-Way Set-Associative Cache : 2 sets with 2 blocks each Fully Associative Cache : 4 blocks Simulation: Direct-Mapped Cache: Access Address Index Cache Content Hit/Miss 1 0 0 0 Miss 2 8 0 8 Miss 3 6 2 8, 6 Miss 4 5 1 8, 6, 5 Miss 5 10 2 8, 10, 5 Miss 6 15 3 8, 10, 5, 15 Miss 7 8 0 8, 10, 5, 15 Hit 8 0 0 0, 10, 5, 15 Miss 9 8 0 8, 10, 5, 15 Miss 10 6 2 8, 6, 5, 15 Miss 11 5 1 8, 6, 5, 15 Hit 12 10 2 8, 10, 5, 15 Miss 13 15 3 8, 10, 5, 15 Hit 14 8 0 8, 10, 5, 15 Hit Direct-Mapped Cache Hits: 3 Two-Way Set-Associative Cache: Access Address Index Set Content Hit/Miss 1 0 0 (0, -) Miss 2 8 0 (0, 8) Miss 3 6 1 (0, 8), (6, -) Miss 4 5 1 (0, 8), (6, 5) Miss 5 10 0 (10, 8), (6, 5) Miss 6 15 1 (10, 8), (6, 15) Miss 7 8 0 (10, 8), (6, 15) Hit 8 0 0 (0, 8), (6, 15) Miss 9 8 0 (0, 8), (6, 15) Hit 10 6 1 (0, 8), (6, 15) Hit 11 5 1 (0, 8), (5, 1...
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Quetion 6 : Consider the "in-order-issue/in-order-completion" execution sequence shown in f In Figure Decode OWE Execute 12 12 12 14 16 13 16 13 15 15 16 Write 024/06/02 11 3 4 11 12 13 13 N 15 16 a. Identify the most likely reason why I could not enter the execute fourth cycle. stage until the [2] b. Will "in-order issue/out-of-order completion" or "out-of-order issue/out-of-order completion" fix this? If so, which? Explain

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Answer:   a. Identify the most likely reason why I could not enter the execute stage until the fourth cycle. One likely reason an instruction couldn't enter the execute stage until the fourth cycle is due to data hazards or resource conflicts: 1. Data Hazards: If the instruction depends on the result of a previous instruction that hasn't completed yet, it cannot proceed to the execute stage. This is often referred to as a Read After Write (RAW) hazard. 2. Resource Conflicts: If the required functional unit for execution (e.g., an ALU) is occupied by another instruction, the instruction will have to wait until the resource becomes available. b. Will "in-order issue/out-of-order completion" or "out-of-order issue/out-of-order completion" fix this? If so, which? Explain In-order issue/out-of-order completion  might help if the problem is related to instructions that can complete earlier being delayed by instructions that take longer to execute. This allows the...
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