Milan Bakotra

Answer:   a. Identify the most likely reason why I could not enter the execute stage until the fourth cycle. One likely reason an instruction couldn't enter the execute stage until the fourth cycle is due to data hazards or resource conflicts: 1. Data Hazards: If the instruction depends on the result of a previous instruction that hasn't completed yet, it cannot proceed to the execute stage. This is often referred to as a Read After Write (RAW) hazard. 2. Resource Conflicts: If the required functional unit for execution (e.g., an ALU) is occupied by another instruction, the instruction will have to wait until the resource becomes available. b. Will "in-order issue/out-of-order completion" or "out-of-order issue/out-of-order completion" fix this? If so, which? Explain In-order issue/out-of-order completion  might help if the problem is related to instructions that can complete earlier being delayed by instructions that take longer to execute. This allows the

  a. Consider a machine which supports the following two instruction schedules for R class and I class instructions. Assume an instruction mix of 70% R class and 30% I class instructions. Assume that IF steps take 30 nano seconds, MEM steps of instruction execution require 50 nanoseconds and the other steps require 40 nanoseconds 0 1 2 3 4 R Class IF ID EX WB I Class IF ID EX MEM WB For a multi-cycle implementation, i. What is the minimum clock cycle time? ii. How long does sit take to execute 200 instructions in nanoseconds? b. Given a deeply pipelined processor and a branch-target buffer for conditional branches only, assuming a misprediction penalty of 5 cycles and a buffer miss penalty of 4 cycles, 95% hit rate and 90% accuracy, and 20% branch frequency. How much faster is the processor with the BTB vs. a processor that has a fixed 4-cycle branch penalty? ANSWER: Part (a): i. Minimum Clock Cycle Time: The minimum