Que 1:A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 20 clock cycles. Thereafter, it takes 25 clock cycles to transfer each byte. The microprocessor is clocked at a rate of 20 GHz. a. Determine the length of the instruction cycle for the case of a string of 128 bytes. b. What is the worst-case delay for acknowledging an interrupt if the instruction is non- interruptible? c. Repeat part (b) assuming the instruction can be interrupted at the beginning of each byte transfer.

Answer:

Given Data:

• Clock rate of the microprocessor: 20 GHz (which is $20\times 10^9$ cycles per second).
• Initial fetching and decoding time: 20 clock cycles.
• Time to transfer each byte: 25 clock cycles.
• Number of bytes to be transferred: 128 bytes.

Part (a): Length of the Instruction Cycle

1. Fetching and Initial Decoding:

   • This step takes 20 clock cycles.

2. Transferring Each Byte:

   • Each byte transfer takes 25 clock cycles.
   • For 128 bytes, total cycles for transfer = 128 bytes * 25 clock cycles/byte = 3200 clock cycles.

3. Total Length of the Instruction Cycle:

   • Total clock cycles = Initial fetching and decoding cycles + Transfer cycles
   • Total clock cycles = 20 cycles + 3200 cycles = 3220 clock cycles.

4. Convert Clock Cycles to Time:

   • Clock speed = 20 GHz = $20\times 10^9$ cycles/second.
   • Time per cycle = $\frac{1}{20\times 10^9}$ seconds.
   • Total time for the instruction cycle = Total clock cycles * Time per cycle
   • Total time = 3220 cycles * $\frac{1}{20\times 10^9}$ seconds/cycle
   • Total time = $\frac{3220}{20\times 10^9}$ seconds
   • Total time = $\frac{3220}{20\times 10^9}$ seconds
   • Total time = $1.61\times 10^{-7}$ seconds
   • Total time = 161 nanoseconds (ns).

So, the length of the instruction cycle for transferring a string of 128 bytes is 161 ns.

Part (b): Worst-case Delay for Acknowledging an Interrupt (Non-interruptible Instruction)

• If the instruction is non-interruptible, the worst-case delay for acknowledging an interrupt is the total time taken by the instruction cycle.
• From part (a), we have already determined this time to be 161 ns.

Part (c): Worst-case Delay for Acknowledging an Interrupt (Interruptible at Each Byte Transfer)

• If the instruction can be interrupted at the beginning of each byte transfer, the worst-case scenario for the delay would be just before a new byte transfer starts.
• In this case, the maximum delay for acknowledging an interrupt would be the time taken to transfer one byte after the initial fetching and decoding time.

1. Time for Initial Fetching and Decoding:

   • This is 20 clock cycles.

2. Time to Transfer One Byte:

   • This is 25 clock cycles.

3. Total Worst-case Delay:

   • Total cycles = Initial fetching and decoding cycles + Time for one byte transfer
   • Total cycles = 20 cycles + 25 cycles = 45 clock cycles.

4. Convert Clock Cycles to Time:

   • Time for 45 cycles = 45 cycles * $\frac{1}{20\times 10^9}$ seconds/cycle
   • Time = $\frac{45}{20\times 10^9}$ seconds
   • Time = $2.25\times 10^{-9}$ seconds
   • Time = 2.25 nanoseconds (ns).

So, the worst-case delay for acknowledging an interrupt, if the instruction can be interrupted at the beginning of each byte transfer, is 2.25 ns.