Quetion 7:a. Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and 100 latencies t1,t2, and t3 such that t1=t3=3t2/4=2t3. If the longest pinnan into two pipeline stages of equal latency, Find the new frequency in GHz, ignoring delays in the pipeline registers. b. A particular system is controlled by a an operator through commands entered from a keyboard. The average number of commands entered in an 6-hour interval is 80. Suppose the processor scans the keyboard every 100 ms. how many times will the keyboard be checked in an 6-hour period? C. Let DS=3080H, CS=0000H, SI=0008H and IP=00FFH.What the physical address of the instruction and data that is fetched? d. How many Memory chips of size 512K X 8 are needed. to develop a a memory of si size 8M X 32 Show the address range .

Answer:

Given:

Let's first find the relationship between the latencies $𝑡 1, 𝑡 2, 𝑡 3$ :

Using $𝑡 2 = \frac{4 𝑡 1}{3}$ :

𝑡 3 = \frac{\frac{4 𝑡 1}{3}}{2} = \frac{4 𝑡 1}{6} = \frac{2 𝑡 1}{3}

Now, since $𝑡 1 = 𝑡 3$ , let:

𝑡 1 = 𝑡 3 = 𝑡

and

𝑡 2 = 2 𝑡 3 = 2 𝑡

The latencies are $𝑡 1 = 𝑡$ , $𝑡 2 = 2 𝑡$ , $𝑡 3 = 𝑡$ .

Now, the longest pipeline stage:

𝑡 2 = 2 𝑡

If we split the longest stage (which is $𝑡 2 = 2 𝑡$ ) into two stages of equal latency, each stage would have:

New latency = \frac{𝑡 2}{2} = \frac{2 𝑡}{2} = 𝑡

The pipeline stages now are:

𝑡 1 = 𝑡, 𝑡 2 = 𝑡, 𝑡 3 = 𝑡, 𝑡 4 = 𝑡 (new stage after splitting)

Since all pipeline stages are now $𝑡$ , the new pipeline latency is $𝑡$ .

The original processor frequency is 3 GHz, corresponding to a time period $𝑇 = \frac{1}{3 \times 1 0^{9}}$ seconds.

Since the original longest stage $𝑡 2 = 2 𝑡$ sets the time period:

2 𝑡 = \frac{1}{3 \times 1 0^{9}}

𝑡 = \frac{1}{6 \times 1 0^{9}}

With the new pipeline stages, each stage is now $𝑡$ :

𝑡 = \frac{1}{6 \times 1 0^{9}}

The new frequency:

New frequency = \frac{1}{𝑡} = 6 GHz

So, the new frequency is 6 GHz.

Given:

Number of scans per second:
$Scans per second = \frac{1}{100 ms} = \frac{1}{0.1 seconds} = 10 scans per second$
Total seconds in 6 hours:
$6 hours = 6 \times 3600 seconds = 21600 seconds$
Total scans in 6 hours:
$Total scans = 21600 seconds \times 10 scans per second = 216000 scans$

So, the keyboard will be checked 216,000 times in a 6-hour period.

Given:

Physical address of the instruction:
$Physical Address = CS \times 10 𝐻 + IP$ $Physical Address = 0000 𝐻 \times 10 𝐻 + 00 𝐹 𝐹 𝐻 = 00 𝐹 𝐹 𝐻$
Physical address of the data:
$Physical Address = DS \times 10 𝐻 + SI$ $Physical Address = 3080 𝐻 \times 10 𝐻 + 0008 𝐻 = 30800 𝐻 + 0008 𝐻 = 30808 𝐻$

So, the physical address of the instruction is 00FFH and the physical address of the data is 30808H.

Given:

Convert sizes to bytes:
- Memory chip size: $512 𝐾 \times 8$ bits = $512 \times 1024 \times 8$ bits = $4, 194, 304$ bits
- Desired memory size: $8 𝑀 \times 32$ bits = $8 \times 1024 \times 1024 \times 32$ bits = $268, 435, 456$ bits
Number of chips needed:
- Each chip provides 512K x 8 bits.
- Total bits per chip: $512 \times 1024 \times 8$ = 4,194,304 bits
- Total number of chips required: $Number of chips = \frac{268, 435, 456 bits}{4, 194, 304 bits per chip} = 64$

Since each chip provides an 8-bit width and we need a 32-bit width, we need 4 chips for each bit of the desired 32-bit memory:

Number of chips needed = 4 \times 16 = 64

So, we need 64 chips.

Address Range:

Each chip is 512K (524288 locations) and with 8 chips being used for each byte, the address range would be: $0 𝑥 00000 to 0 𝑥 7 𝐹 𝐹 𝐹 𝐹 (for each 8-chip set)$

Thus, for a memory of size $8 𝑀 \times 32$ , the address range for each 32-bit wide section would be:

0 𝑥 00000 to 0 𝑥 7 𝐹 𝐹 𝐹 𝐹 𝐹

Milan Bakotra