Quetion 7:a. Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and 100 latencies t1,t2, and t3 such that t1=t3=3t2/4=2t3. If the longest pinnan into two pipeline stages of equal latency, Find the new frequency in GHz, ignoring delays in the pipeline registers. b. A particular system is controlled by a an operator through commands entered from a keyboard. The average number of commands entered in an 6-hour interval is 80. Suppose the processor scans the keyboard every 100 ms. how many times will the keyboard be checked in an 6-hour period? C. Let DS=3080H, CS=0000H, SI=0008H and IP=00FFH.What the physical address of the instruction and data that is fetched? d. How many Memory chips of size 512K X 8 are needed. to develop a a memory of si size 8M X 32 Show the address range .

 Answer:

Part (a): New Frequency of the Processor

Given:

• Processor frequency: 3 GHz
• Three-stage pipeline with latencies $𝑡1,𝑡2,𝑡3$
• $𝑡1=𝑡3$
• $𝑡1=\frac{3𝑡2}{4}$
• $𝑡2=2𝑡3$

Let's first find the relationship between the latencies $𝑡1,𝑡2,𝑡3$:

1. From $𝑡1=\frac{3𝑡2}{4}$:

   $$𝑡2=\frac{4𝑡1}{3}$$

2. From $𝑡2=2𝑡3$:

   $$𝑡3=\frac{𝑡2}{2}$$

Using $𝑡2=\frac{4𝑡1}{3}$:

$$𝑡3=\frac{\frac{4𝑡1}{3}}{2}=\frac{4𝑡1}{6}=\frac{2𝑡1}{3}$$

Now, since $𝑡1=𝑡3$, let:

$$𝑡1=𝑡3=𝑡$$

and

$$𝑡2=2𝑡3=2𝑡$$

The latencies are $𝑡1=𝑡$, $𝑡2=2𝑡$, $𝑡3=𝑡$.

Now, the longest pipeline stage:

$$𝑡2=2𝑡$$

If we split the longest stage (which is $𝑡2=2𝑡$) into two stages of equal latency, each stage would have:

$$\text{New latency}=\frac{𝑡2}{2}=\frac{2𝑡}{2}=𝑡$$

The pipeline stages now are:

$$𝑡1=𝑡,𝑡2=𝑡,𝑡3=𝑡,𝑡4=𝑡(\text{new stage after splitting})$$

Since all pipeline stages are now $𝑡$, the new pipeline latency is $𝑡$.

The original processor frequency is 3 GHz, corresponding to a time period $𝑇=\frac{1}{3\times 10^9}$ seconds.

Since the original longest stage $𝑡2=2𝑡$ sets the time period:

$$2𝑡=\frac{1}{3\times 10^9}$$

$$𝑡=\frac{1}{6\times 10^9}$$

With the new pipeline stages, each stage is now $𝑡$:

$$𝑡=\frac{1}{6\times 10^9}$$

The new frequency:

$$\text{New frequency}=\frac{1}{𝑡}=6\text{ GHz}$$

So, the new frequency is 6 GHz.

Part (b): Keyboard Scan Frequency

Given:

• Average number of commands entered in 6 hours: 80
• Processor scans the keyboard every 100 ms

1. Number of scans per second:

   $$\text{Scans per second}=\frac{1}{100\text{ ms}}=\frac{1}{0.1\text{ seconds}}=10\text{ scans per second}$$

2. Total seconds in 6 hours:

   $$6\text{ hours}=6\times 3600\text{ seconds}=21600\text{ seconds}$$

3. Total scans in 6 hours:

   $$\text{Total scans}=21600\text{ seconds}\times 10\text{ scans per second}=216000\text{ scans}$$

So, the keyboard will be checked 216,000 times in a 6-hour period.

Part (c): Physical Address Calculation

Given:

• Data Segment (DS) = 3080H
• Code Segment (CS) = 0000H
• Source Index (SI) = 0008H
• Instruction Pointer (IP) = 00FFH

1. Physical address of the instruction:

   $$\text{Physical Address}=\text{CS}\times 10𝐻+\text{IP}$$
   $$\text{Physical Address}=0000𝐻\times 10𝐻+00𝐹𝐹𝐻=00𝐹𝐹𝐻$$

2. Physical address of the data:

   $$\text{Physical Address}=\text{DS}\times 10𝐻+\text{SI}$$
   $$\text{Physical Address}=3080𝐻\times 10𝐻+0008𝐻=30800𝐻+0008𝐻=30808𝐻$$

So, the physical address of the instruction is 00FFH and the physical address of the data is 30808H.

Part (d): Number of Memory Chips Needed

Given:

• Memory chip size = 512K x 8
• Desired memory size = 8M x 32

1. Convert sizes to bytes:

   • Memory chip size: $512𝐾\times 8$ bits = $512\times 1024\times 8$ bits = $4,194,304$ bits
   • Desired memory size: $8𝑀\times 32$ bits = $8\times 1024\times 1024\times 32$ bits = $268,435,456$ bits

2. Number of chips needed:

   • Each chip provides 512K x 8 bits.
   • Total bits per chip: $512\times 1024\times 8$ = 4,194,304 bits
   • Total number of chips required:
     $$\text{Number of chips}=\frac{268,435,456\text{ bits}}{4,194,304\text{ bits per chip}}=64$$

Since each chip provides an 8-bit width and we need a 32-bit width, we need 4 chips for each bit of the desired 32-bit memory:

$$\text{Number of chips needed}=4\times 16=64$$

So, we need 64 chips.

Address Range:

• Each chip is 512K (524288 locations) and with 8 chips being used for each byte, the address range would be:
  $$0𝑥00000\text{ to }0𝑥7𝐹𝐹𝐹𝐹\text{ (for each 8-chip set)}$$

Thus, for a memory of size $8𝑀\times 32$, the address range for each 32-bit wide section would be:

$$0𝑥00000\text{ to }0𝑥7𝐹𝐹𝐹𝐹𝐹$$